1. Field of the Invention
Embodiments of the invention generally relate to electronic design automation and, more specifically, to a method and apparatus for implementing a task-based interface in a logic verification system.
2. Description of the Related Art
In electronic design automation (EDA), functional verification is the task of verifying that a logic design conforms to its specification before the logic design is manufactured as integrated circuits (ICs). Typically, a test design is established to perform verification processes on the logic design (referred to as a “test bench”). Logic designs and test designs may be described using various languages, such as hardware description languages (HDLs) or other more abstract languages (e.g., synthesizable SystemC). Functional verification can be performed using a simulation acceleration or emulation process, where the logic design is mapped into a hardware accelerator or emulator to provide a design under verification (DUV), and the test bench is executed by a simulator on a computer or workstation. Such simulation acceleration/emulation systems allow a design to run much faster than pure software simulation on only a general-purpose computer or workstation.
Typically, the test bench communicates with the DUV using a signal-based interface implemented over a communication link between the computer and the hardware accelerator. The signal-based interface can be defined using low-level signal ports in the test and logic designs. Some languages, such as Verilog HDL, include the capability of higher level inter-module communication using task/function calls (“task interface”). Use of such a task interface between the test bench and the DUV can achieve significant increases in communication speed over a signal-based interface. However, there are several technical challenges for supporting a task interface across the simulator/accelerator partition. The definition of a task/function in the test bench can consume simulation time. The caller of a task can invoke a task by non-blocking fork operations to create dynamic threads. Multiple processes can call the same task instance concurrently. Moreover, the number of calling processes is not known at compile time. Such challenges have heretofore prevented the use of a task interface between the test bench and DUV in a simulation acceleration/emulation system.
Accordingly, there exists a need in the art for a method and apparatus for implementing a task-based interface in a logic verification system.